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Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability.
Prasad Vernekar
Nithin Kumar Yernad Balachandra
Vasantha Moodabettu Harishchandra
Published in:
ISVLSI (2019)
Keyphrases
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low voltage
random access memory
cmos technology
low power
design considerations
power line
read write
write operations
power management
leakage current
power consumption
high speed
image processing
parallel computing
parallel processing
cost effective
digital images
image sequences