Rahul Shrestha

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 47

Top Topics

Cognitive Radio

Eigenvalues And Eigenvectors

Improved Accuracy

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Shakti Singh, Rahul Shrestha
Ultra-Low Sensing-Time and Hardware-Efficient Spectrum Sensor for Data Fusion-Based Cooperative Cognitive-Radio Network. IEEE Trans. Consumer Electron. 70 (1) (2024)
Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury
Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (7) (2024)
Shakti Singh, Rahul Shrestha
A New Hardware-Efficient and Low Sensing-Time Cooperative Spectrum-Sensor for High-Throughput Cognitive-Radio Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (1) (2024)
Elivander J. T. Pereira, Dayan Adionel Guimarães, Rahul Shrestha
VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (5) (2024)
Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury
Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator. VLSID (2024)
Anuj Verma, Rahul Shrestha
Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes. IEEE Trans. Veh. Technol. 72 (1) (2023)
Dayan Adionel Guimarães, Elivander J. T. Pereira, Rahul Shrestha
Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks. IEEE Trans. Veh. Technol. 72 (9) (2023)
Rahul Sharma, Rahul Shrestha, Satinder K. Sharma
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (3) (2023)
Meghvern Pathak, Rahul Shrestha
Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems. VLSID (2023)
Rohit B. Chaurasiya, Rahul Shrestha
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network. IEEE Trans. Very Large Scale Integr. Syst. 30 (2) (2022)
Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury
A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications. ISVLSI (2022)
Rahul Sharma, Rahul Shrestha, Satinder K. Sharma
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method. IEEE Trans. Very Large Scale Integr. Syst. 30 (8) (2022)
Rohit B. Chaurasiya, Rahul Shrestha
Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network. IEEE Trans. Consumer Electron. 68 (3) (2022)
Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 30 (12) (2022)
Sumanth Gudaparthi, Rahul Shrestha
Selective register-file cache: an energy saving technique for embedded processor architecture. Des. Autom. Embed. Syst. 26 (2) (2022)
Lalit Kumar, Rahul Shrestha
A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal. J. Signal Process. Syst. 94 (12) (2022)
Kumari Suravi, Rahul Shrestha
High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems. ISVLSI (2022)
Rohit B. Chaurasiya, Rahul Shrestha
Area-Efficient and Scalable Data-Fusion Based Cooperative Spectrum Sensor for Cognitive Radio. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Rahul Shrestha
A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications. IEEE Trans. Very Large Scale Integr. Syst. 29 (1) (2021)
Rohit B. Chaurasiya, Rahul Shrestha
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network. IEEE Trans. Very Large Scale Integr. Syst. 29 (4) (2021)
Rohit B. Chaurasiya, Rahul Shrestha
Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network. ISCAS (2021)
Anuj Verma, Rahul Shrestha
Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture. IEEE Trans. Circuits Syst. II Express Briefs 68 (8) (2021)
Rohit B. Chaurasiya, Rahul Shrestha
Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (4) (2020)
Anuj Verma, Rahul Shrestha
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio. VLSI Design (2020)
Rahul Shrestha, Shubham Sanjay Telgote
A Short Sensing-Time Cyclostationary Feature Detection Based Spectrum Sensor for Cognitive Radio Network. ISCAS (2020)
Anuj Verma, Rahul Shrestha
A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard. ISCAS (2020)
Rohit B. Chaurasiya, Rahul Shrestha
Hardware-Efficient and Low Sensing-Time VLSI-Architecture of MED Based Spectrum Sensor for Cognitive Radio. ISCAS (2019)
Rohit B. Chaurasiya, Rahul Shrestha
Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2019)
Rahul Shrestha, Pooja Bansal, Srikant Srinivasan
High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio. VLSI Design (2019)
Rahul Shrestha, Abhijit Sahoo
High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder. IEEE Trans. Circuits Syst. II Express Briefs (7) (2019)
Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers
Parameterized Posit Arithmetic Hardware Generator. ICCD (2018)
Mahesh S. Murty, Rahul Shrestha
Reconfigurable and Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks. IEEE Trans. Circuits Syst. II Express Briefs (8) (2018)
Mahesh S. Murty, Rahul Shrestha
Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network. VLSI Design (2018)
Mahesh S. Murty, Rahul Shrestha
Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network. IET Circuits Devices Syst. 12 (5) (2018)
Rahul Shrestha, Ashutosh Sharma
VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates. VLSI-SoC (2018)
Rahul Shrestha, Ashutosh Sharma
Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices. VDAT (2018)
B. Dinesh Kumar, Sumit Pandey, Puneet Arora, Rahul Shrestha
A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector. ISED (2017)
Sumanth Gudaparthi, Rahul Shrestha
Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization. VDAT (2017)
Naman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury
A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications. VDAT (2017)
Rahul Shrestha
High-speed and low-power VLSI-architecture for inexact speculative adder. VLSI-DAT (2017)
Naman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury
PGMA: An algorithmic approach for multi-objective hardware software partitioning. Microprocess. Microsystems 54 (2017)
Rahul Kurzekar, Hardik Arora, Rahul Shrestha
Embedded Hardware Prototype for Gas Detection and Monitoring System in Android Mobile Platform. iNIS (2017)
Mahesh S. Murty, Rahul Shrestha
VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation. ISVLSI (2016)
Vijaya Kumar Kanchetla, Rahul Shrestha, Roy Paily
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards. IET Circuits Devices Syst. 10 (2) (2016)
Rahul Shrestha, Roy Paily
Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders. Circuits Syst. Signal Process. 35 (8) (2016)
Rahul Shrestha, Vinay Swargam, Mahesh S. Murty
Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives. VDAT (2016)
Rahul Shrestha, Utkarsh Rastogiy
Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier. VLSI Design (2016)
Rahul Shrestha, Roy P. Paily
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder. J. Signal Process. Syst. 81 (2) (2015)
John W. Burris, Rahul Shrestha, Bibek Gautam, Bibidh Bista
Machine learning for the activation of contraflows during hurricane evacuation. GHTC (2015)
Rahul Shrestha, Roy P. Paily
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder. J. Low Power Electron. 11 (3) (2015)
Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy P. Paily
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2015)
Rahul Shrestha, Roy Paily
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique. ISED (2014)
Rahul Shrestha, Roy P. Paily
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Rahul Shrestha, Roy P. Paily
A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder. ICACCI (2013)
Rahul Shrestha, Roy P. Paily
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. VLSI Design (2013)
Rahul Shrestha, Roy P. Paily
Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard. IET Commun. 7 (12) (2013)
Rahul Shrestha, Roy P. Paily
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding. VDAT (2012)