High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems.
Kumari SuraviRahul ShresthaPublished in: ISVLSI (2022)
Keyphrases
- low density parity check
- low latency
- high throughput
- vlsi architecture
- low complexity
- vlsi implementation
- ldpc codes
- decoding algorithm
- low power
- microarray
- real time
- distributed video coding
- wireless communication
- channel coding
- error correction
- high speed
- data acquisition
- physical layer
- highly efficient
- fading channels
- power consumption
- computational complexity
- source coding
- unequal error protection
- wavelet transform