Roy Paily

Publication Activity (10 Years)

Years Active: 2008-2022
Publications (10 Years): 16

Top Topics

Vision Algorithms

Haar Wavelet Transform

Top Venues

Circuits Syst. Signal Process.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Rohit Lorenzo, Roy Paily
Half-selection disturbance free 8T low leakage SRAM cell. Int. J. Circuit Theory Appl. 50 (5) (2022)
Satyajit Bora, Roy Paily
Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers. Circuits Syst. Signal Process. 41 (2) (2022)
Satyajit Bora, Roy Paily
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications. IEEE Trans. Circuits Syst. II Express Briefs 68 (6) (2021)
Soham Talukder, Rajan Singh, Satyajit Bora, Roy Paily
An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform. Circuits Syst. Signal Process. 39 (7) (2020)
Rohit Lorenzo, Roy Paily
Low Power 10T SRAM Cell with Improved Stability Solving Soft Error Issue. TENCON (2019)
Vimal Kumar Singh Yadav, Siddhanta Roy, Gayatri Natu, Roy Paily
Fabrication of Back to Back Schottky Micro-Diodes Using Silver Nanoparticle Film and Zinc Oxide Nanowire Mat for Biological Interactions. TENCON (2019)
Pralay Chakrabarty, Siddhanta Roy, Roy Paily
Analysis of Electromagnetic Actuation System for Different Coil Topologies. TENCON (2019)
Manchi Pavan Kumar, Roy Paily, Anup Kumar Gogoi
Low-Power Digital Baseband Transceiver Design for UWB Physical Layer of IEEE 802.15.6 Standard. IEEE Trans. Ind. Informatics 13 (5) (2017)
Saroj Mondal, Roy Paily
Efficient Solar Power Management System for Self-Powered IoT Node. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Saroj Mondal, Roy Paily
On-Chip Photovoltaic Power Harvesting System With Low-Overhead Adaptive MPPT for IoT Nodes. IEEE Internet Things J. 4 (5) (2017)
Vijaya Kumar Kanchetla, Rahul Shrestha, Roy Paily
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards. IET Circuits Devices Syst. 10 (2) (2016)
Rahul Shrestha, Roy Paily
Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders. Circuits Syst. Signal Process. 35 (8) (2016)
Vinaya M. M., Roy Paily, Anil Mahanta
Power Optimization of LNA for LTE Receiver. VLSI Design (2016)
Vaddi Chandra Sekhar, Satyajit Bora, Monalisa Dash, Manchi Pavan Kumar, S. Josephine, Roy Paily
Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms. VLSI Design (2016)
Vinaya M. M., Roy Paily, Anil Mahanta
Analysis and design of moderate inversion based low power low-noise amplifier. IET Comput. Digit. Tech. 10 (5) (2016)
Manchi Pavan Kumar, Roy Paily, Anup Kumar Gogoi
Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard. VLSI Design (2016)
Sunil P. Joshi, Roy Paily
Distributed Arithmetic based Split-Radix FFT. J. Signal Process. Syst. 75 (1) (2014)
Rahul Shrestha, Roy Paily
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique. ISED (2014)
R. K. Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar, Roy Paily
An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network. VDAT (2013)
Vinay M. M., Roy Paily, Anil Mahanta
Gain, NF and IIP3 Budgeting of LTE Receiver Front End. VLSI Design (2013)
Abdul Raouf Khalid, Roy Paily
Fpga Implementation of High Speed and Low Power Architectures for Image Segmentation using Sobel Operators. J. Circuits Syst. Comput. 21 (7) (2012)
Sudheer Kurakula, A. S. D. P. Sudhansh, Roy Paily, Samarendra Dandapat
Design of QRS Detection and Heart Rate Estimation System on FPGA. ACC (4) (2011)
Depak Balemarthy, Roy Paily
A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning. ISLPED (2008)