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Satyajit Bora
ORCID
Publication Activity (10 Years)
Years Active: 2016-2022
Publications (10 Years): 4
Top Topics
Xilinx Virtex
Vision Algorithms
Real Time Stereo
Sparse Matrices
Top Venues
Circuits Syst. Signal Process.
IEEE Trans. Circuits Syst. II Express Briefs
VLSI Design
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Publications
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Satyajit Bora
,
Roy Paily
Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers.
Circuits Syst. Signal Process.
41 (2) (2022)
Satyajit Bora
,
Roy Paily
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs
68 (6) (2021)
Soham Talukder
,
Rajan Singh
,
Satyajit Bora
,
Roy Paily
An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform.
Circuits Syst. Signal Process.
39 (7) (2020)
Vaddi Chandra Sekhar
,
Satyajit Bora
,
Monalisa Dash
,
Manchi Pavan Kumar
,
S. Josephine
,
Roy Paily
Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms.
VLSI Design
(2016)