VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder.
Rahul ShresthaRoy P. PailyPublished in: J. Low Power Electron. (2015)
Keyphrases
- hardware implementation
- energy efficient
- vlsi design
- high speed
- fpga implementation
- wireless sensor networks
- energy consumption
- sensor networks
- signal processing
- efficient implementation
- image processing algorithms
- hardware architecture
- parallel architecture
- design methodology
- base station
- memory management
- energy efficiency
- field programmable gate array
- routing algorithm
- data transmission
- general purpose
- database
- sensor nodes
- routing protocol
- data streams
- pattern recognition
- image processing
- databases