Roy P. Paily

Publication Activity (10 Years)

Years Active: 2009-2016
Publications (10 Years): 8

Top Topics

Wireless Communication

Comparative Study

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Saroj Mondal, Roy P. Paily
An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer. IEEE Trans. Circuits Syst. II Express Briefs (3) (2016)
Saroj Mondal, Roy P. Paily
An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems. VLSI Design (2016)
Rahul Shrestha, Roy P. Paily
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder. J. Signal Process. Syst. 81 (2) (2015)
Saroj Mondal, Roy P. Paily
An efficient on-chip energy processing circuit for micro-scale energy harvesting systems. VDAT (2015)
Vinay M. M., Roy P. Paily, Anil Mahanta
A low-power subthreshold LNA for mobile applications. VDAT (2015)
Rahul Shrestha, Roy P. Paily
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder. J. Low Power Electron. 11 (3) (2015)
Vinaya M. M., Roy P. Paily, Anil Mahanta
A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2015)
Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy P. Paily
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2015)
Fradaric Joseph, Kiran Francis, Archita Hore, Siddhanta Roy, S. Josephine, Roy P. Paily
An efficient hardware architecture for stereo disparity estimation. VDAT (2014)
Rahul Shrestha, Roy P. Paily
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Nagesh Ch, Roy P. Paily
Fabrication and Testing of an Osmotic Pressure Sensor for Glucose Sensing Application. Micromachines 5 (3) (2014)
Rahul Shrestha, Roy P. Paily
A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder. ICACCI (2013)
Rahul Shrestha, Roy P. Paily
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. VLSI Design (2013)
Rahul Shrestha, Roy P. Paily
Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard. IET Commun. 7 (12) (2013)
Ratul Kumar Baruah, Roy P. Paily
A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance. VDAT (2013)
Rahul Shrestha, Roy P. Paily
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding. VDAT (2012)
Amrita Brahmachari, Roy P. Paily
Low power 2.4 GHz RF transmitter for satellite subsystem using CORDIC based frequency translator. WOCN (2012)
K. C. Narasimhamurthy, Roy P. Paily
Fabrication and characterisation of high-performance and high-current back-gate thin-film field-effect transistors using sorted single-walled carbon nanotubes. IET Circuits Devices Syst. 5 (5) (2011)
K. C. Narasimhamurthy, Roy P. Paily
Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes. VLSI Design (2011)
K. C. Narasimhamurthy, Roy P. Paily
Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects. VLSI Design (2009)