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Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding.

Rahul ShresthaRoy P. Paily
Published in: VDAT (2012)
Keyphrases
  • shift register
  • hardware implementation
  • high speed
  • efficient implementation
  • implementation issues
  • random number generator
  • case study
  • relevance feedback
  • design methodology
  • hardware architecture
  • turbo codes