A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio.
Anuj VermaRahul ShresthaPublished in: VLSI Design (2020)
Keyphrases
- low density parity check
- vlsi architecture
- low complexity
- physical layer
- ldpc codes
- distributed video coding
- vlsi implementation
- low power
- error correction
- channel coding
- real time
- decoding algorithm
- wireless communication
- distributed source coding
- message passing
- error resilience
- turbo codes
- multipath
- rate allocation
- unequal error protection
- rate distortion
- high speed
- multiscale
- image sequences