Farhad Merchant

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 84

Top Topics

Hardware Designs

Top Venues

Publications

Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay
Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG. VLSID (2024)
Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID (2024)
Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn
Error Detection and Correction Codes for Safe In-Memory Computations. CoRR (2024)
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC (2024)
Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant
In-Memory Mirroring: Cloning Without Reading. CoRR (2024)
Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. CoRR (2024)
Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn
Error Detection and Correction Codes for Safe In-Memory Computations. ETS (2024)
Simranjeet Singh, Farhad Merchant, Sachin B. Patkar
Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms. CoRR (2024)
Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. CoRR (2023)
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. CoRR (2023)
Anouar Nechi, Lukas Groth, Saleh Mulhem, Farhad Merchant, Rainer Buchty, Mladen Berekovic
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing? ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant
Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS (2023)
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. NEWCAS (2023)
Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR (2023)
Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. NEWCAS (2023)
Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin Patkar, Farhad Merchant
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR (2023)
Niraj N. Sharma, Riya Jain, Mohana Madhumita Pokkuluri, Sachin B. Patkar, Rainer Leupers, Rishiyur S. Nikhil, Farhad Merchant
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. J. Syst. Archit. 135 (2023)
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR (2023)
Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant
Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. NANOARCH (2023)
Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. VLSI-SoC (2023)
Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. CoRR (2023)
Gokulnath Rajendran, Furqan Zahoor, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay
PR-PUF: A Reconfigurable Strong RRAM PUF. VLSI-SoC (2023)
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR (2023)
Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. ISLPED (2023)
Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. CoRR (2023)
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. 15 (4) (2023)
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin Patkar, Anupam Chattopadhyay, Farhad Merchant
Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. ASP-DAC (2023)
Anand Raj, Nikhitha Avula, Pabitra Das, Dominik Sisejkovic, Farhad Merchant, Amit Acharyya
DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking. ISCAS (2023)
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. LATS (2022)
Michael Gansen, Jie Lou, Florian Freye, Tobias Gemmeke, Farhad Merchant, Albert Zeyer, Mohammad Zeineldeen, Ralf Schlüter, Xin Fan
Discrete Steps towards Approximate Computing. ISQED (2022)
Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil, Qi Shu, Peter Schüffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krüger, Leticia Pöhls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grützmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max C. Lemme, Rainer Leupers, Rainer Waser
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE (2022)
Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. CoRR (2022)
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin Patkar, Anupam Chattopadhyay, Farhad Merchant
Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. CoRR (2022)
Simranjeet Singh, Srinivasu Bodapati, Sachin Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant
PA-PUF: A Novel Priority Arbiter PUF. VLSI-SoC (2022)
Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE (2022)
Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. CoRR (2022)
Felix Staudigl, Farhad Merchant, Rainer Leupers
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security. IEEE Des. Test 39 (2) (2022)
Farhad Merchant
Security as an Important Ingredient in Neuromorphic Engineering. ISVLSI (2022)
Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
pHGen: A pH-Based Key Generation Mechanism Using ISFETs. HOST (2022)
Simranjeet Singh, Srinivasu Bodapati, Sachin Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant
PA-PUF: A Novel Priority Arbiter PUF. CoRR (2022)
Melvin Galicia, Farhad Merchant, Rainer Leupers
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. ISQED (2022)
Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers
An Investigation on Inherent Robustness of Posit Data Representation. CoRR (2021)
Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR (2021)
Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE (2021)
Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD (2021)
Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSI Design (2021)
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR (2021)
Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer
Nano Security: From Nano-Electronics to Secure Systems. DATE (2021)
Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant
Brightening the Optical Flow through Posit Arithmetic. CoRR (2021)
Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems. IEEE Access 9 (2021)
Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant
Brightening the Optical Flow through Posit Arithmetic. ISQED (2021)
Melvin Galicia, Farhad Merchant, Rainer Leupers
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. CoRR (2021)
Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR (2021)
Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers
An Investigation on Inherent Robustness of Posit Data Representation. VLSI Design (2021)
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. 17 (3) (2021)
Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR (2021)
Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC (2021)
Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR (2021)
Jure Vreca, Karl J. X. Sturm, Ernest Gungl, Farhad Merchant, Paolo Bientinesi, Rainer Leupers, Zmago Brezocnik
Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit. IEEE Access 8 (2020)
Riya Jain, Niraj Sharma, Farhad Merchant, Sachin Patkar, Rainer Leupers
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. CoRR (2020)
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR (2020)
Andre Guntoro, Cecilia De la Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar
Next Generation Arithmetic for Edge Computing. DATE (2020)
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Sascha Kegreiß
Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS (2020)
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß
A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES (2020)
Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems. CoRR (2020)
Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
Protecting the Integrity of Processor Cores with Logic Encryption. SoCC (2019)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
Applying Modified Householder Transform to Kalman Filter. VLSI Design (2019)
Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. ACM Great Lakes Symposium on VLSI (2019)
Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Volker Kiefer
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. VLSI-DAT (2019)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSI Design (2019)
Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. ETS (2019)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. ARC (2018)
Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers
Parameterized Posit Arithmetic Hardware Generator. ICCD (2018)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR (2018)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design. CoRR (2018)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. IEEE Trans. Parallel Distributed Syst. 29 (8) (2018)
Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. Parallel Process. Lett. 27 (3-4) (2017)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design. CoRR (2016)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. VLSI Design (2016)
Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. CoRR (2016)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR (2016)
Farhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. VLSI Design (2016)
Debjyoti Bhattacharjee, Farhad Merchant, Anupam Chattopadhyay
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays. VLSI-SoC (2016)
Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. VLSI Design (2015)
Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. VLSI-SoC (2014)
Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). VLSI Design (2014)
Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. ICSAMOS (2014)
Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. 60 (7) (2014)
Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay
Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. ASAP (2014)
Alok Baluni, Farhad Merchant, S. K. Nandy, Srinivasan Balakrishnan
A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support. ISED (2011)