Vikas Rana

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 52

Top Topics

Positive And Negative

Error Detection And Correction

Experimental Verification

Top Venues

Publications

Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay
Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG. VLSID (2024)
Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID (2024)
Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn
Error Detection and Correction Codes for Safe In-Memory Computations. CoRR (2024)
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC (2024)
Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant
In-Memory Mirroring: Cloning Without Reading. CoRR (2024)
Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn
Error Detection and Correction Codes for Safe In-Memory Computations. ETS (2024)
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. CoRR (2023)
Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant
Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS (2023)
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. NEWCAS (2023)
Seokki Son, Camilla La Torre, Andreas Kindsmüller, Vikas Rana, Stephan Menzel
A Study of the Electroforming Process in 1T1R Memory Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR (2023)
Vasileios G. Ntinas, Dharmik Patel, Yongmin Wang, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff
A Simplified Variability-Aware VCM Memristor Model for Efficient Circuit Simulation. SMACD (2023)
Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin Patkar, Farhad Merchant
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR (2023)
Yongmin Wang, Kristoffer Schnieders, Vasileios Ntinas, Alon Ascoli, Felix Cüppers, Susanne Hoffmann-Eifert, Stefan Wiefels, Ronald Tetzlaff, Vikas Rana, Stephan Menzel
Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task. NANOARCH (2023)
N. Schmitt, Alon Ascoli, Ioannis Messaris, Ahmet Samil Demirkol, Vasileios G. Ntinas, Dimitrios Prousalis, Ronald Tetzlaff, S. Nikolaidis, Stephan Menzel, Vikas Rana
Exploration of Bistable Oscillatory Dynamics in a Memristor from Forschungszentrum Jülich. MOCAST (2023)
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR (2023)
Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant
Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. NANOARCH (2023)
Gokulnath Rajendran, Furqan Zahoor, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay
PR-PUF: A Reconfigurable Strong RRAM PUF. VLSI-SoC (2023)
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR (2023)
Vasileios G. Ntinas, Yongmin Wang, Ahmet Samil Demirkol, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff
Design and Analysis of Isolated Voltage-Mode Memristor Cellular Nonlinear Network Cells. ISCAS (2023)
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. 15 (4) (2023)
Vasileios G. Ntinas, Alon Ascoli, Ioannis Messaris, Yongmin Wang, Vikas Rana, Stephan Menzel, Ronald Tetzlaff
Toward Simplified Physics-Based Memristor Modeling of Valence Change Mechanism Devices. IEEE Trans. Circuits Syst. II Express Briefs 69 (5) (2022)
Yongmin Wang, Alon Ascoli, Ronald Tetzlaff, Vikas Rana, Stephan Menzel
Performance Analysis of Memristive-CNN based on a VCM Device Model. ISCAS (2022)
Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil, Qi Shu, Peter Schüffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krüger, Leticia Pöhls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grützmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max C. Lemme, Rainer Leupers, Rainer Waser
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE (2022)
Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE (2022)
Christopher Bengel, Stefan Wiefels, Vikas Rana, Hsin-Yu Chen, Qing-Tai Zhao, Rainer Waser, Henriette Padberg, Fengben Xi, Stephan Menzel
Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory. ISCAS (2022)
Wonjoo Kim, Dirk J. Wouters, Rainer Waser, Vikas Rana
Tuning the Memory Window of TaOx ReRAM Using the RF Sputtering Power. ISCAS (2021)
Vivek Tyagi, Vikas Rana
Adaptive Forward Body Bias Voltage Generator. VLSI Design (2021)
Tim Kempen, Rainer Waser, Vikas Rana
50x Endurance Improvement in TaOx RRAM by Extrinsic Doping. IMW (2021)
Christopher Bengel, Anne Siemon, Vikas Rana, Stephan Menzel
Implementation of Multinary Łukasiewicz Logic Using Memristive Devices. ISCAS (2021)
Vivek Tyagi, Shivam Kalla, Vikas Rana
Negative Voltage Generator and Current DAC Based Regulator For Flash Memory. VLSI Design (2021)
Vikas Rana, Teddy Le Nguyen, Veera Raghava, Prahlad G. Menon
Intelligent patient monitoring for proactive alerting of key personnel in intensive care: A single-center study. EMBC (2021)
Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR (2021)
Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Marco Pasotti
Power Efficient Sense Amplifier For Emerging Non Volatile Memories. VLSI Design (2020)
Vikas Rana, Shivam Kalla
Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping Efficiency. SoCC (2020)
Camilla La Torre, Andreas Kindsmüller, Seokki Son, Rainer Waser, Vikas Rana, Stephan Menzel
A Compact Model for the Electroforming Process of Memristive Devices. ECCTD (2020)
Prakhar Shukla, Prabhat Singh, Tushar Maheshwari, Anuj Grover, Vikas Rana
A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP. ICECS (2020)
Marcella Carissimi, Ritesh Mukherjee, Vivek Tyagi, Fabio Disegni, Davide Manfrè, Cesare Torti, Daniele Gallinari, Sandro Rossi, Andrea Gambero, Donatella Brambilla, Paola Zuliani, Riccardo Zurla, Alessandro Cabrini, Guido Torelli, Marco Pasotti, Chantal Auricchio, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Stefano Zanchi, Vikas Rana, Preeti Mishra
2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications. ESSCIRC (2019)
Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Riccardo Zurla, Marco Pasotti
Current DAC Based -40dB PSRR Configurable Output LDO in BCD Technology. VLSI Design (2019)
Vikas Rana
CMOS Oscillator Having Stable Frequency with Process, Temperature and Voltage Variation. VLSI Design (2018)
Marco Pasotti, Riccardo Zurla, Marcella Carissimi, Chantal Auricchio, Donatella Brambilla, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Daniele Gallinari, Cristina Mazzaglia, Vikas Rana, Alessandro Cabrini, Guido Torelli
A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications. IEEE J. Solid State Circuits 53 (7) (2018)
Vikas Rana, Rohan Sinha
Stress Relaxed Multiple Output High-Voltage Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs (2) (2018)
Vikas Rana, Marco Pasotti, Marcella Carissimi
Row decoder for embedded Phase Change Memory using low voltage transistors. Microelectron. J. 81 (2018)
Vikas Rana
Area Efficient NMOS Based Positive and Negative Voltage Multiplier. ISVLSI (2018)
Vikas Rana
Switched Capacitor based Area Efficient Positive and Negative Voltage Multiplier. APCCAS (2018)
Vikas Rana, Abhishek Mittal
Switched Capacitor based High Positive and Negative Voltage Charge-pump using Sample and Hold technique. APCCAS (2018)
Marco Pasotti, Marcella Carissimi, Chantal Auricchio, Donatella Brambilla, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Daniele Gallinari, Cristina Mazzaglia, Vikas Rana, Riccardo Zurla, Alessandro Cabrini, Guido Torelli
A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications. ESSCIRC (2017)
Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana
A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM. VDAT (2017)
Vikas Rana, Marco Pasotti, F. Desantis
Single charge-pump generating high positive and negative voltages driving common load. VLSI-SoC (2017)
Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana
A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator. VDAT (2017)
Wonjoo Kim, Dirk J. Wouters, Stephan Menzel, Christian Rodenbucher, Rainer Waser, Vikas Rana
Lowering forming voltage and forming-free behavior of Ta2O5 ReRAM devices. ESSDERC (2016)
Amit Chhabra, Vikas Rana
-1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI. VLSI Design (2016)
Rainer Waser, Stephan Menzel, Vikas Rana
Recent progress in redox-based resistive switching. ISCAS (2012)