-1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI.
Amit ChhabraVikas RanaPublished in: VLSI Design (2016)
Keyphrases
- power consumption
- nm technology
- cmos technology
- low power
- random access memory
- power management
- power dissipation
- embedded dram
- design considerations
- high speed
- silicon on insulator
- power saving
- low voltage
- image sensor
- power reduction
- human body
- management system
- focal plane
- data center
- packet switching
- low cost
- real time
- analog vlsi
- design methodology
- cmos image sensor
- dynamic random access memory