Nalesh Sivanandan

Publication Activity (10 Years)

Years Active: 2013-2021
Publications (10 Years): 15

Top Topics

Fast Fourier Transform

Convolutional Neural Network

Hardware Architecture

Radial Basis Function

Top Venues

IET Comput. Digit. Tech.

Publications

Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala
Hardware Acceleration of SpMV Multiplier for Deep Learning. VDAT (2021)
Abi K. Krishnan, M. H. Supriya, Nalesh Sivanandan
A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA. VDAT (2021)
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture. IEEE Trans. Very Large Scale Integr. Syst. 27 (12) (2019)
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. VLSI Design (2019)
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan
based two-dimensional FFT architecture with efficient data reordering scheme. IET Comput. Digit. Tech. 13 (2) (2019)
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan
Efficient Hardware Acceleration of Convolutional Neural Networks. SoCC (2019)
S. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi
algorithm with efficient output reordering. DTIS (2018)
Mahnaz Mohammadi, Akhil Krishna, Nalesh Sivanandan, S. K. Nandy
A Hardware Architecture for Radial Basis Function Neural Network Classifier. IEEE Trans. Parallel Distributed Syst. 29 (3) (2018)
S. Kala, Debdeep Paul, Babita R. Jose, Nalesh Sivanandan
Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA. ISED (2018)
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
Energy aware synthesis of application kernels through composition of data-paths on a CGRA. Integr. 58 (2017)
Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. VLSI Design (2016)
Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Compiling HPC Kernels for the REDEFINE CGRA. HPCC/CSS/ICESS (2015)
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. 11 (3) (2015)
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. iNIS (2015)
Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. VLSI Design (2015)
Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. ICSAMOS (2014)
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED (2014)
Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. 60 (7) (2014)
S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS (2013)