Kavitha T. Madhu

Publication Activity (10 Years)

Years Active: 2014-2021
Publications (10 Years): 6

Top Topics

Multiple Kernel Learning

Svm Classification

Resource Allocation

Top Venues

PARMA-DITAM@HiPEAC

Publications

Aditi Saluja, Arnab Mitra, Ankur Deshwal, Kavitha T. Madhu, Ujjawal Chugh, Seungwon Lee, Joonho Song
Autotuning LSTM for Accelerated Execution on Edge. ISCAS (2021)
Kavitha T. Madhu, Saptarsi Das, Abhishek Tyagi, Ankur Deshwal, Joonho Song, Seungwon Lee
Transport Triggered near Memory Accelerator for Deep Learning. ISCAS (2021)
Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, Francois Neumann, Philippe Baufreton
™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress). CASES (2017)
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
Energy aware synthesis of application kernels through composition of data-paths on a CGRA. Integr. 58 (2017)
Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. VLSI Design (2016)
Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Krishna C. Madhava, S. K. Nandy, Ranjani Narayan
Flexible resource allocation and management for application graphs on ReNÉ MPSoC. PARMA-DITAM@HiPEAC (2016)
Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Compiling HPC Kernels for the REDEFINE CGRA. HPCC/CSS/ICESS (2015)
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. iNIS (2015)
Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. ICSAMOS (2014)
Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. 60 (7) (2014)