S. Kala

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 13

Top Topics

Energy Efficient

Fast Fourier Transform

Convolutional Neural Networks

Top Venues

Int. J. Embed. Syst.

Publications

M. A. Muneeb, Nalesh S, S. Kala
A physically unclonable function architecture with multiple responses on FPGA. Int. J. Embed. Syst. 16 (1) (2023)
Abhinav Kalvacherla, Rachana George, Nalesh S, S. Kala
Approximate CNN on FPGA Using Toom-Cook Multiplier. iSES (2023)
Noble G, Nalesh S, S. Kala
MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles. VLSID (2023)
Noble G, Nalesh S, S. Kala
Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA. APCCAS (2023)
Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala
Hardware Acceleration of SpMV Multiplier for Deep Learning. VDAT (2021)
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture. IEEE Trans. Very Large Scale Integr. Syst. 27 (12) (2019)
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. VLSI Design (2019)
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan
based two-dimensional FFT architecture with efficient data reordering scheme. IET Comput. Digit. Tech. 13 (2) (2019)
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan
Efficient Hardware Acceleration of Convolutional Neural Networks. SoCC (2019)
S. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi
algorithm with efficient output reordering. DTIS (2018)
S. Kala, Debdeep Paul, Babita R. Jose, Nalesh Sivanandan
Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA. ISED (2018)
S. Kala, Babita R. Jose, Debdeep Paul, Jimson Mathew
A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform. VDAT (2018)
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. 11 (3) (2015)
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED (2014)
S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS (2013)