Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture.
Anuj VermaRahul ShresthaPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2021)
Keyphrases
- high throughput
- decoding algorithm
- ldpc codes
- low latency
- microarray
- non binary
- genome wide
- low density parity check
- data acquisition
- biological data
- real time
- vlsi architecture
- low cost
- mass spectrometry data
- vlsi implementation
- proteomic data
- gene expression
- mass spectrometry
- error correction
- data management
- search space
- computational complexity