Deepak Kachave

Publication Activity (10 Years)

Years Active: 2016-2019
Publications (10 Years): 11

Top Topics

Spatial And Temporal

Design Space Exploration

Application Specific

Top Venues

Microelectron. Reliab.

Future Gener. Comput. Syst.

IET Comput. Digit. Tech.

Publications

Anirban Sengupta, Deepak Kachave, Dipanjan Roy
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (4) (2019)
Anirban Sengupta, Deepak Kachave
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis. Future Gener. Comput. Syst. 80 (2018)
Deepak Kachave, Anirban Sengupta
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters]. IEEE Consumer Electron. Mag. 7 (2) (2018)
Anirban Sengupta, Deepak Kachave
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores. iSES (2018)
Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation. IET Comput. Digit. Tech. 12 (6) (2018)
Anirban Sengupta, Deepak Kachave
Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath. IEEE Trans. Aerosp. Electron. Syst. 54 (3) (2018)
Anirban Sengupta, Deepak Kachave
-unit transient for loop based control data flow graphs during physically aware high level synthesis. Microelectron. Reliab. 74 (2017)
Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha
Reliability and Threat Analysis of NBTI Stress on DSP Cores. iNIS (2017)
Deepak Kachave, Anirban Sengupta
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors. Microelectron. Reliab. 60 (2016)
Deepak Kachave, Anirban Sengupta
Protecting Ownership of Reusable IP Core Generated during High Level Synthesis. iNIS (2016)
Anirban Sengupta, Deepak Kachave
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. ISVLSI (2016)