Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores.
Anirban SenguptaDeepak KachavePublished in: iSES (2018)
Keyphrases
- fault tolerant
- simulated annealing
- fault tolerance
- distributed systems
- level parallelism
- state machine
- steady state
- general purpose
- signal processing
- evolutionary algorithm
- load balancing
- genetic algorithm
- digital signal processing
- high availability
- software systems
- transactional memory
- multi core processors
- interconnection networks
- code generation
- address space
- fault isolation
- digital signal processor