Abir J. Mondal

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 14

Top Topics

Skeleton Extraction

Mathematical Formulation

Gate Dielectrics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Kuntal Chakraborty, Jai Gopal Pandey, Abir J. Mondal
Design and Analysis of an Area and Power Efficient Programmable Delay Cell. VLSID (2024)
Kuntal Chakraborty, Abir J. Mondal
On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ. Integr. 96 (2024)
Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder
Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. RADIOELEKTRONIKA (2023)
Mithilesh Kumar, Alak Majumder, Abir J. Mondal
Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current. J. Circuits Syst. Comput. 31 (16) (2022)
Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya
A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. Integr. 87 (2022)
Anirban Tarafdar, Abir J. Mondal, Uttam Kumar Bera, B. K. Bhattacharyya
A PVT aware differential delay circuit and its performance variation due to power supply noise. Integr. 76 (2021)
Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. Integr. 58 (2017)
Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. Integr. 58 (2017)
Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
A Design Methodology for MOS Current Mode Logic VCO. iNIS (2017)
Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
W Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications. J. Low Power Electron. 13 (3) (2017)
Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. iNIS (2017)
Paromita Bhattacharjee, Abir J. Mondal, Alak Majumder
A constraint driven technique for MOS amplifier design. VDAT (2016)
Rama Prasad Acharya, Abir J. Mondal, Alak Majumder
A method to design a comparator for sampled data processing applications. VDAT (2016)
Sandeep Kumar Singh, Abir J. Mondal, Alak Majumder
Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs. LATS (2015)