Pritam Bhattacharjee

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 12

Top Topics

Gate Dielectrics

Contour Extraction

Top Venues

J. Circuits Syst. Comput.

RADIOELEKTRONIKA

Publications

Pritam Bhattacharjee, Alak Majumder
Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. VLSID (2024)
Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder
Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. RADIOELEKTRONIKA (2023)
Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder
A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. Circuits Syst. Signal Process. 40 (4) (2021)
Pritam Bhattacharjee, Alak Majumder
A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application. J. Circuits Syst. Comput. 28 (7) (2019)
Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder
Data-Dependent Clock Gating approach for Low Power Sequential System. CoRR (2018)
Alak Majumder, Pritam Bhattacharjee, Tushar Dhabal Das
A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips. J. Circuits Syst. Comput. 27 (9) (2018)
Pritam Bhattacharjee, Bipasha Nath, Alak Majumder
LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications. CoRR (2018)
Alak Majumder, Pritam Bhattacharjee
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip. iNIS (2017)
Pritam Bhattacharjee, Kunal Das, Arijit Dey, Debashis De, Swarnendu Kumar Chakraborty
Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell. J. Low Power Electron. 13 (2) (2017)
Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das
A 90 nm leakage control transistor based clock gating for low power flip flop applications. MWSCAS (2016)
Pritam Bhattacharjee, Alak Majumder
LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. iNIS (2016)