LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications.

Pritam Bhattacharjee Bipasha Nath Alak Majumder

Published in: CoRR (2018)

Keyphrases

multistage
power dissipation
low power
flip flops
power consumption
high speed
low cost
power reduction
single stage
dynamic programming
cmos technology
digital signal processing
optimal policy
energy efficiency
image sensor
mixed signal
hardware and software
fuzzy rules
low voltage
supply chain
real time