Alak Majumder

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 34

Top Topics

Mathematical Formulation

Top Venues

J. Circuits Syst. Comput.

Publications

Anirban Tarafdar, Azharuddin Sheikh, Pinki Majumder, Abhijit Baidya, Alak Majumder, Bidyut K. Bhattacharyya, Uttam Kumar Bera
Enhancing intrusion detection using wireless sensor networks: A novel ahp-madm aggregated multiple type 3 fuzzy logic-based k-barriers prediction system. Peer Peer Netw. Appl. 17 (3) (2024)
Pritam Bhattacharjee, Alak Majumder
Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. VLSID (2024)
Jyoti Kandpal, Tika Ram Pokhrel, Shalu Saini, Alak Majumder
A variation resilient keeper design for high performance domino logic applications. Integr. 88 (2023)
Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder
Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. RADIOELEKTRONIKA (2023)
Barnali Chowdhury, Shashank Awasthi, Mohammad Arif Bin Jalil, Alak Majumder, Sanjeev Kumar Metya
Ti:LiNbO3 Based EO-MZI Count Optimized Design of Reversible Peres Gate. RADIOELEKTRONIKA (2023)
Tika Ram Pokhrel, Alak Majumder
MOS Application. APCCAS (2023)
Mithilesh Kumar, Alak Majumder, Abir J. Mondal
Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current. J. Circuits Syst. Comput. 31 (16) (2022)
Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya
A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. Integr. 87 (2022)
Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder
A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. Circuits Syst. Signal Process. 40 (4) (2021)
Madhusudan Maiti, Alak Majumder, Shubhro Chakrabartty, Hanjung Song, Bidyut K. Bhattacharyya
Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range. Microelectron. J. 98 (2020)
Shashank Awasthi, Saurav Sharma, Sanjeev Kumar Metya, Alak Majumder
Electro-optic Reversible Toffoli Gate with Optimal Count of LiNbO3 Mach-Zehnder Interferometers. NorCAS (2020)
Madhusudan Maiti, Shubhro Chakrabartty, Alaaddin Al-Shidaifat, Hanjung Song, Bidyut K. Bhattacharyya, Alak Majumder
A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking Range. NorCAS (2020)
Pritam Bhattacharjee, Alak Majumder
A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application. J. Circuits Syst. Comput. 28 (7) (2019)
Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Nivedita Laskar, Suman Debnath, Alak Majumder, Bidyut K. Bhattacharyya
A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. J. Circuits Syst. Comput. 27 (3) (2018)
Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder
Data-Dependent Clock Gating approach for Low Power Sequential System. CoRR (2018)
Alak Majumder, Pritam Bhattacharjee, Tushar Dhabal Das
A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips. J. Circuits Syst. Comput. 27 (9) (2018)
Pritam Bhattacharjee, Bipasha Nath, Alak Majumder
LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications. CoRR (2018)
Bipasha Nath, Alak Majumder
Binary Counter Based Gated Clock Tree for Integrated CPU Chip. iNIS (2017)
Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. Integr. 58 (2017)
Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. Integr. 58 (2017)
Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
A Design Methodology for MOS Current Mode Logic VCO. iNIS (2017)
Alak Majumder, Bidyut K. Bhattacharyya
Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect. Turkish J. Electr. Eng. Comput. Sci. 25 (2017)
Shirsha Ghosh, Alak Majumder, Joyeeta Goswami, Abhishek Kumar, Saraju P. Mohanty, Bidyut K. Bhattacharyya
Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment. IEEE Consumer Electron. Mag. 6 (1) (2017)
Alak Majumder, Pritam Bhattacharjee
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip. iNIS (2017)
Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
W Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications. J. Low Power Electron. 13 (3) (2017)
Alak Majumder
Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip. J. Low Power Electron. 13 (4) (2017)
Alak Majumder, Joyeeta Goswami, Shirsha Ghosh, Rishu Shrivastawa, Saraju P. Mohanty, Bidyut K. Bhattacharyya
Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users. IEEE Consumer Electron. Mag. 6 (2) (2017)
Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. iNIS (2017)
Paromita Bhattacharjee, Abir J. Mondal, Alak Majumder
A constraint driven technique for MOS amplifier design. VDAT (2016)
Rama Prasad Acharya, Abir J. Mondal, Alak Majumder
A method to design a comparator for sampled data processing applications. VDAT (2016)
Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das
A 90 nm leakage control transistor based clock gating for low power flip flop applications. MWSCAS (2016)
Pritam Bhattacharjee, Alak Majumder
LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. iNIS (2016)
Joyeeta Goswami, Shirsha Ghosh, Shivaditya Katiyar, Alak Majumder
Development of a prototype to detect speed limit violation for better traffic management. IC3 (2015)
Sandeep Kumar Singh, Abir J. Mondal, Alak Majumder
Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs. LATS (2015)