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A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%.

Nivedita LaskarSuman DebnathAlak MajumderBidyut K. Bhattacharyya
Published in: J. Circuits Syst. Comput. (2018)
Keyphrases
  • high speed
  • noisy data
  • signal to noise ratio
  • logic programming
  • color images
  • modal logic
  • noise reduction
  • noise level
  • gaussian noise
  • classical logic
  • chip design