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Nivedita Laskar
Publication Activity (10 Years)
Years Active: 2018-2018
Publications (10 Years): 1
Top Topics
Modal Logic
Noise Reduction
Top Venues
J. Circuits Syst. Comput.
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Publications
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Nivedita Laskar
,
Suman Debnath
,
Alak Majumder
,
Bidyut K. Bhattacharyya
A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%.
J. Circuits Syst. Comput.
27 (3) (2018)