Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.
Pritam BhattacharjeeG. Naveen GoudVipin K. SinghVijay P. YadavAbir J. MondalAlak MajumderPublished in: RADIOELEKTRONIKA (2023)
Keyphrases
- low power
- cmos technology
- power consumption
- nm technology
- leakage current
- low voltage
- high speed
- low cost
- flip flops
- circuit design
- power reduction
- power dissipation
- electron microscopy
- action selection
- high density
- comparative analysis
- vlsi circuits
- gate dielectrics
- database
- power management
- image sensor
- data center
- x ray
- video sequences
- reinforcement learning
- genetic algorithm
- real time