Login / Signup

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.

Alak MajumderMonalisa DasSuraj Kumar SawAbir J. MondalBidyut K. Bhattacharyya
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2019)
Keyphrases
  • design process
  • case study
  • high density
  • single chip
  • physical design
  • response time
  • circuit design
  • evolvable hardware
  • communication networks
  • functional verification
  • analog to digital converter