Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.
Alak MajumderMonalisa DasSuraj Kumar SawAbir J. MondalBidyut K. BhattacharyyaPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2019)