LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder.
Pritam BhattacharjeeAlak MajumderPublished in: iNIS (2016)
Keyphrases
- low power
- power consumption
- logic circuits
- high speed
- power dissipation
- low power consumption
- single chip
- low cost
- vlsi architecture
- digital signal processing
- gate array
- cmos technology
- design process
- power reduction
- ultra low power
- general purpose
- power saving
- wireless transmission
- image sensor
- design methodology
- hardware and software
- high power
- computer simulation