Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip.
Alak MajumderPublished in: J. Low Power Electron. (2017)
Keyphrases
- high speed
- cmos technology
- low power
- analog vlsi
- high density
- low cost
- circuit design
- tree structure
- noisy data
- noise level
- power consumption
- duty cycle
- noise reduction
- missing data
- gallium arsenide
- signal to noise ratio
- power dissipation
- focal plane
- real time
- charge coupled device
- evolvable hardware
- metal oxide semiconductor