A 90 nm leakage control transistor based clock gating for low power flip flop applications.
Pritam BhattacharjeeAlak MajumderTushar Dhabal DasPublished in: MWSCAS (2016)
Keyphrases
- power dissipation
- low power
- clock gating
- power consumption
- cmos technology
- power reduction
- flip flops
- nm technology
- high speed
- low cost
- digital signal processing
- logic circuits
- low power consumption
- control strategy
- power management
- power saving
- low voltage
- finite state machines
- energy efficiency
- image sensor
- mixed signal
- sensor networks