N. S. Murty

Publication Activity (10 Years)

Years Active: 1997-2020
Publications (10 Years): 7

Top Topics

Error Correction

Top Venues

Microprocess. Microsystems

Circuits Syst. Signal Process.

Publications

M. Vinodhini, N. S. Murty, T. K. Ramesh
Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC. IEEE Access 8 (2020)
Kolasani Sahithi, N. S. Murty
Delay based Physical Unclonable Function for Hardware Security and Trust. ICACCI (2018)
T. Siva Teja, T. Sai Kiran, T. V. V. Satya Narayana, M. Vinodhini, N. S. Murty
Joint Crosstalk Avoidance with Multiple Bit Error Correction Coding Technique for NoC Interconnect. ICACCI (2018)
K. Vrinda, N. S. Murty, Dhanesh G. Kurup
Performance of Vector Fitting Algorithm Applied to Bandpass and Baseband Systems. Circuits Syst. Signal Process. 37 (11) (2018)
M. Vinodhini, N. S. Murty
Reliable low power NoC interconnect. Microprocess. Microsystems 57 (2018)
Supriya Rajagopal, M. Vinodhini, N. S. Murty
Multi-Bit Error Correction Coding with Crosstalk Avoidance Using Parity Sharing Technique for NoC. iSES (2018)
Rajani Suthar, Kirti S. Pande, N. S. Murty
Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique. iNIS (2017)
Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty
IBM's Blue Logic Design Methodology-Circuits and Physical Design. VLSI Design (2001)
R. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik
Effective Heuristics for Timing Driven Constructive Placement. VLSI Design (1997)