Pallabi Sarkar

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 7

Top Topics

High Level Synthesis

Hardware Software

Design Space Exploration

Parametric Optimization

Top Venues

IEEE Consumer Electron. Mag.

Publications

Nameshwari Verma, Pallabi Sarkar
System Complexity Reduction Using 3-D Matrices and Novel Logic Gates. ICCCNT (2023)
Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography. ICCE-Berlin (2020)
Pallabi Sarkar, Dipanjan Roy, Anirban Sengupta, Mrinal Kanti Naskar
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 8 (1) (2019)
Dipanjan Roy, Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar
Optimizing DSP Cores Using Design Transformation [Hardware Matters]. IEEE Consumer Electron. Mag. 7 (4) (2018)
Anirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar
Obfuscation of Fault Secured DSP Design Through Hybrid Transformation. ISVLSI (2018)
Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar
A Firefly Algorithm Driven Approach for High Level Synthesis. iNIS (2017)
Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar
Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 6 (4) (2017)
Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar
GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis. CCECE (2015)
Tulasi Krishna, Priyam Sachdeva, Suraj Kumar Dhanuka, Mohit Gagrani, Pallabi Sarkar
A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design. ICACCI (2013)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design. Microprocess. Microsystems 36 (4) (2012)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels. Swarm Evol. Comput. 7 (2012)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis. CCECE (2011)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications. CCECE (2011)
Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis. ACAI (2011)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
Integrated design space exploration based on power-performance trade-off using genetic algorithm. ACAI (2011)