Reza Sedaghat

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 9

Top Topics

Security Architecture

Optimization Problems

High Level Synthesis

Top Venues

Trans. Comput. Sci.

Swarm Evol. Comput.

J. Hardw. Syst. Secur.

Publications

Prathap Siddavaatam, Reza Sedaghat, Nahid Sahelgozin
A Novel Machine Learning Framework for Covid-19 Image Classification with Bio-heuristic Optimization. Trans. Comput. Sci. 39 (2022)
Prathap Siddavaatam, Reza Sedaghat
A New Bio-heuristic Hybrid Optimization for Constrained Continuous Problems. Trans. Comput. Sci. 38 (2021)
Noel Jose Thengappurackal Laiju, Reza Sedaghat, Prathap Siddavaatam
Novel Hybrid GWO-WOA and BAT-PSO Algorithms for Solving Design Optimization Problems. Trans. Comput. Sci. 38 (2021)
Prathap Siddavaatam, Reza Sedaghat
A New Adaptive Security Architecture with Extensible Computation Complexity for Generic Ciphers. J. Hardw. Syst. Secur. 3 (4) (2019)
Prathap Siddavaatam, Reza Sedaghat
Grey Wolf Optimizer Driven design space exploration: A novel framework for multi-objective trade-off in architectural synthesis. Swarm Evol. Comput. 49 (2019)
Prathap Siddavaatam, Reza Sedaghat
A Delta-Diagram Based Synthesis for Cross Layer Optimization Modeling of IoT. Trans. Comput. Sci. 33 (2018)
Prathap Siddavaatam, Reza Sedaghat, Aakriti Tarun Sharma
intel-LEACH: An optimal framework for node selection using dynamic clustering for wireless sensor networks. ICITST (2017)
Prathap Siddavaatam, Reza Sedaghat, Min Hsuan Cheng
An adaptive security framework with extensible computational complexity for cipher systems. ICITST (2016)
Min Hsuan Cheng, Reza Sedaghat, Prathap Siddavaatam
A New Adaptable Construction of Modulo Addition with Scalable Security for Stream Ciphers. NSS (2016)
Anirban Sengupta, Reza Sedaghat
Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget. CCECE (2015)
Anirban Sengupta, Reza Sedaghat
Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget. Microelectron. Reliab. 55 (6) (2015)
Behnaz Abdoli, Reza Sedaghat, Manuchehr Taghiloo
Optimized Predictive Zonal Search (OPZS) for block-based motion estimation. Signal Process. Image Commun. 39 (2015)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design. Microprocess. Microsystems 36 (4) (2012)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels. Swarm Evol. Comput. 7 (2012)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis. CCECE (2011)
Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe
Switch-level emulation of strength-base soft error detection. Microelectron. Reliab. 51 (3) (2011)
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems. Microelectron. Reliab. 51 (2) (2011)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications. CCECE (2011)
Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis. ACAI (2011)
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
Integrated design space exploration based on power-performance trade-off using genetic algorithm. ACAI (2011)
Anirban Sengupta, Reza Sedaghat
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration. ISQED (2011)
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP). Microprocess. Microsystems 35 (4) (2011)
Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe
Switch-level soft error emulation for SET-induced pulses of variable strengths. Microelectron. J. 41 (10) (2010)
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
Rapid design space exploration for multi parametric optimization of VLSI designs. ISCAS (2010)
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective. Microelectron. Reliab. 50 (3) (2010)
Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures. ISCAS (2010)
M. Reza Javaheri, Reza Sedaghat
Strength violation effect on soft-error detection in sub-micron technology. Microelectron. Reliab. 50 (7) (2010)
M. Reza Javaheri, Reza Sedaghat
Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies. Microelectron. Reliab. 49 (2) (2009)
Peter Ming-Han Lee, Reza Sedaghat
FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration. Microelectron. Reliab. 48 (10) (2008)
M. Reza Javaheri, Reza Sedaghat
A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies. CSICC (2008)
Mayuri Kunchwar, Reza Sedaghat, Vadim Geurkov
Dynamic behavior of resistive faults in nanometer technology. Microelectron. Reliab. 47 (12) (2007)
Reza Sedaghat, Mayuri Kunchwar, Raha Abedi, M. Reza Javaheri
Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates. Microelectron. Reliab. 46 (12) (2006)
Hyunsuk Moon, Reza Sedaghat
FPGA-Based adaptive digital predistortion for radio-over-fiber links. Microprocess. Microsystems 30 (3) (2006)
M. Reza Javaheri, Reza Sedaghat, Leo Kant, Jason Zalev
Verification and fault synthesis algorithm at switch-level. Microprocess. Microsystems 30 (4) (2006)
Reza Sedaghat
A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation. ISCAS (5) (2003)