Rajit Karmakar

Publication Activity (10 Years)

Years Active: 2014-2022
Publications (10 Years): 21

Top Topics

Data Compression

Cellular Automata

Discrete Dynamical Systems

Top Venues

Publications

Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
A Cellular Automata Guided Finite-State-Machine Watermarking Strategy for IP Protection of Sequential Circuits. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay
Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits. IEEE Trans. Circuits Syst. II Express Briefs (3) (2020)
Rajit Karmakar, Santanu Chattopadhyay
Hardware IP Protection Using Logic Encryption and Watermarking. ITC (2020)
Rajit Karmakar, Santanu Chattopadhyay
A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access. DATE (2020)
Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection. Integr. 74 (2020)
Rajit Karmakar, Santanu Chattopadhyay
On Securing Scan Obfuscation Strategies Against ScanSAT Attack. ISQED (2020)
Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis. DAC (2019)
Rajit Karmakar, Santanu Chattopadhyay, Mrityunjoy Chakraborty
Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure. ISCAS (2019)
Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay
On Finding Suitable Key-Gate Locations In Logic Encryption. ISCAS (2018)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits. CoRR (2018)
Rajit Karmakar, Santanu Chattopadhyay
Temperature and data size trade-off in dictionary based test data compression. Integr. 57 (2017)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
Enhancing security of logic encryption using embedded key generation unit. ITC-Asia (2017)
Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta
A New Logic Encryption Strategy Ensuring Key Interdependency. VLSI Design (2017)
N. Prasad, Rajit Karmakar, Santanu Chattopadhyay, Indrajit Chakrabarti
Runtime mitigation of illegal packet request attacks in Networks-on-Chip. ISCAS (2017)
Srinivasa Shashank Nuthakki, Rajit Karmakar, Santanu Chattopadhyay, Krishnendu Chakrabarty
Optimization of the IEEE 1687 access network for hybrid access schedules. VTS (2016)
Rajit Karmakar, Santanu Chattopadhyay
Thermal-Safe Schedule Generation for System-on-Chip Testing. VLSI Design (2016)
Rajit Karmakar, Santanu Chattopadhyay
Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling. Integr. 50 (2015)
Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach. VTS (2015)
Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints. ATS (2015)
Rajit Karmakar, Santanu Chattopadhyay
Thermal-Aware Test Data Compression Using Dictionary Based Coding. VLSI Design (2015)
Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model. VDAT (2014)