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An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture.
N. Prasad
Indrajit Chakrabarti
Santanu Chattopadhyay
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
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network on chip
multi processor
routing algorithm
interconnection networks
wireless sensor networks
hardware implementation
network simulator
packet switched
hidden markov models
noisy channel
energy efficient
low cost
fault tolerant
real time
error concealment
data transfer
program execution
dynamic programming