Sagar S. Sabade

Publication Activity (10 Years)

Years Active: 2001-2006
Publications (10 Years): 0

Publications

Sagar S. Sabade, D. M. H. Walker
Estimation of fault-free leakage current using wafer-level spatial information. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Sagar S. Sabade, Duncan M. Hank Walker
IC Outlier Identification Using Multiple Test Metrics. IEEE Des. Test Comput. 22 (6) (2005)
Sagar S. Sabade, D. M. H. Walker
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. VTS (2004)
Sagar S. Sabade, D. M. H. Walker
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. VLSI Design (2004)
Sagar S. Sabade, D. M. H. Walker
-based test methods: A survey. ACM Trans. Design Autom. Electr. Syst. 9 (2) (2004)
Sagar S. Sabade, D. M. H. Walker
data analysis using neighbor current ratios. J. Syst. Archit. 50 (5) (2004)
Sagar S. Sabade, D. M. H. Walker
CROWNE: Current Ratio Outliers with Neighbor Estimator. DFT (2003)
Sagar S. Sabade, D. M. H. Walker
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. VLSI Design (2003)
Sagar S. Sabade, D. M. H. Walker
Use of Multiple IDDQ Test Metrics for Outlier Identification. VTS (2003)
Sagar S. Sabade, D. M. H. Walker
IDDQ Test: Will It Survive the DSM Challenge? IEEE Des. Test Comput. 19 (5) (2002)
Sagar S. Sabade, D. M. H. Walker
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. DFT (2002)
Sagar S. Sabade, D. M. H. Walker
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. VLSI Design (2002)
Sagar S. Sabade, D. M. H. Walker
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. VTS (2002)
Sagar S. Sabade, D. M. H. Walker
Improved wafer-level spatial analysis for I_DDQ limit setting. ITC (2001)