Duncan M. Hank Walker

Publication Activity (10 Years)

Years Active: 1990-2023
Publications (10 Years): 2

Top Topics

Dc Dc Converter

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Avijit Chakraborty, Duncan M. Hank Walker
Topological Heuristics for Scan Test Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (6) (2023)
Swati Chakraborty, Duncan M. Hank Walker
At-Speed Path Delay Test. NATW (2015)
Tengteng Zhang, Duncan M. Hank Walker
Improved power supply noise control for pseudo functional test. VTS (2014)
Tengteng Zhang, Duncan M. Hank Walker
Power supply noise control in pseudo functional test. VTS (2013)
Zheng Wang, Duncan M. Hank Walker
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric. VTS (2009)
Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger
Modeling Power Supply Noise in Delay Testing. IEEE Des. Test Comput. 24 (3) (2007)
Sagar S. Sabade, Duncan M. Hank Walker
IC Outlier Identification Using Multiple Test Metrics. IEEE Des. Test Comput. 22 (6) (2005)
Eunjae Jung, Duncan M. Hank Walker
Reliable energy efficient routing in wireless sensor networks. MASS (2005)
Martin D. Giles, Duane S. Boning, Goodwin R. Chin, Walter C. Dietrich Jr., Michael S. Karasick, Mark E. Law, Purnendu K. Mozumder, Lee R. Nackman, V. T. Rajan, Duncan M. Hank Walker, Robert H. Wang, Alexander S. Wong
Semiconductor wafer representation for TCAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (1) (1994)
Dinesh D. Gaitonde, Duncan M. Hank Walker
Test quality and yield analysis using the DEFAM defect to fault mapper. ICCAD (1993)
Duncan M. Hank Walker, D. S. Nydick
DVLASIC: catastrophic fault yield simulation in a distributed processing environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (6) (1990)