Alexander Fell

Publication Activity (10 Years)

Years Active: 2008-2021
Publications (10 Years): 12

Top Topics

Simulation Tool

Countermeasures

Top Venues

IEEE J. Sel. Top. Signal Process.

Publications

Alexander Fell, Daniel J. Mazure, Teresa C. Garcia, Borja Pérez, Xavier Teruel, Pete Wilson, John D. Davis
The MareNostrum Experimental Exascale Platform (MEEP). Supercomput. Front. Innov. 8 (1) (2021)
Thinh Hung Pham, Ben Marshall, Alexander Fell, Siew-Kei Lam, Daniel Page
XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage. IACR Cryptol. ePrint Arch. 2021 (2021)
Boria Pérez, Alexander Fell, John D. Davis
Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC. DATE (2021)
Thinh Hung Pham, Ben Marshall, Alexander Fell, Siew-Kei Lam, Daniel Page
XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage. ASAP (2021)
Akshay Jain, Pulkit Goel, Shivam Aggarwal, Alexander Fell, Saket Anand
Symmetric $k$-Means for Deep Neural Network Compression and Hardware Acceleration on FPGAs. IEEE J. Sel. Top. Signal Process. 14 (4) (2020)
Alexander Fell, Thinh Hung Pham, Siew-Kei Lam
TAD: time side-channel attack defense of obfuscated source code. ASP-DAC (2019)
Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna
CIDPro: Custom Instructions for Dynamic Program Diversification. FPL (2018)
Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna
CIDPro: Custom Instructions for Dynamic Program Diversification. CoRR (2018)
Praveen Kumar, Alexander Fell, Sachin Mathur
Automated, inter-macro channel space adjustment and optimization for faster design closure. SoCC (2017)
Akshay Jain, Alexander Fell, Saket Anand
A Parallel Architecture for High Frame Rate Stereo using Semi-Global Matching. BMVC (2017)
Manideepa Mukherjee, Alexander Fell, Apala Guha
DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable Architectures. VLSI Design (2017)
Harsh Rawat, K. Bharath, Alexander Fell
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology. SoCC (2017)
Ramandeep Kaur, Alexander Fell, Harsh Rawat
A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI. SoCC (2015)
Alexander Fell, S. K. Nandy, Ranjani Narayan
A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address. SoCC (2015)
Gaurav Narang, Alexander Fell, Prakhar Raj Gupta, Anuj Grover
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems. SoCC (2015)
Alexander Fell, Zoltán Endre Rákossy, Anupam Chattopadhyay
Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures. ReConFig (2014)
Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC (2009)
Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES (2009)
Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan
REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9 (2) (2009)
Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC (2009)
Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan
Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP (2008)
Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP (2008)