G. Surendra

Publication Activity (10 Years)

Years Active: 2001-2008
Publications (10 Years): 0

Publications

Subhasis Banerjee, G. Surendra, S. K. Nandy
On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. J. Syst. Archit. 54 (8) (2008)
Subhasis Banerjee, G. Surendra, S. K. Nandy
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC (2007)
G. Surendra, Subhasis Banerjee, S. K. Nandy
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embed. Comput. 2 (1) (2006)
G. Surendra, Subhasis Banerjee, S. K. Nandy
On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. WMPI (2004)
G. Surendra, Subhasis Banerjee, S. K. Nandy
Power-performance trade-off using pipeline delays. ASP-DAC (2004)
Subhasis Banerjee, G. Surendra, S. K. Nandy
Exploiting program execution phases to trade power and performance for media workload. ASP-DAC (2004)
G. Surendra, Subhasis Banerjee, S. K. Nandy
On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. Int. J. Parallel Program. 31 (6) (2003)
G. Surendra, Subhasis Banerjee, S. K. Nandy
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. DATE (2003)
G. Surendra, S. K. Nandy, Paul Sathya
ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. VLSI Design (2001)