Architecture of Run-Time Reconfigurable Channel Decoder.

Ritesh Rajore S. K. Nandy H. S. Jamadagni

Published in: ICC (2009)

Keyphrases

noisy channel
hardware implementation
fpga implementation
central processing unit
error control
low cost
management system
software architecture
low complexity
data flow
heterogeneous computing
joint source channel
real time
rate allocation
reed solomon
turbo codes
hardware architecture