Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture.
Ritesh RajoreGanesh GargaH. S. JamadagniS. K. NandyPublished in: ASAP (2008)
Keyphrases
- multiprocessor architecture
- mesh connected
- noisy channel
- production system
- binary images
- array processor
- massively parallel
- hidden markov models
- image processing tasks
- decoding algorithm
- viterbi algorithm
- low cost
- processor array
- semantic network
- hardware implementation
- gray scale
- parallel computing
- error control
- knowledge base
- input image
- computational complexity