On-chip memory architecture exploration framework for DSP processor-based embedded system on chip.
T. S. Rajesh KumarR. GovindarajanC. P. RavikumarPublished in: ACM Trans. Embed. Comput. Syst. (2012)
Keyphrases
- high speed
- systolic array
- level parallelism
- dynamic random access memory
- digital signal processors
- embedded systems
- power consumption
- multithreading
- memory management
- memory subsystem
- vlsi implementation
- single chip
- associative memory
- software architecture
- memory access
- parallel architecture
- hardware and software
- main memory