Methodology for low power test pattern generation using activity threshold control logic.
Srivaths RaviV. R. DevanathanRubin A. ParekhjiPublished in: ICCAD (2007)
Keyphrases
- low power
- logic circuits
- power consumption
- low cost
- high speed
- delay insensitive
- single chip
- wireless transmission
- low power consumption
- high power
- digital signal processing
- vlsi circuits
- vlsi architecture
- mixed signal
- power reduction
- gate array
- energy dissipation
- ultra low power
- asynchronous circuits
- real time
- cmos technology
- design methodology
- general purpose
- motion estimation
- image processing