A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath.
V. R. DevanathanSumant KalePublished in: ITC (2016)
Keyphrases
- level parallelism
- dynamic random access memory
- heterogeneous computing
- smart camera
- hardware implementation
- compute intensive
- embedded systems
- loosely coupled
- associative memory
- memory subsystem
- embedded dram
- low cost
- memory hierarchy
- heterogeneous systems
- management system
- memory usage
- processing elements
- memory management
- general purpose
- general purpose processors
- memory requirements
- computing power
- software architecture
- design considerations
- reconfigurable hardware
- parallel architectures
- database systems
- random access
- data structure