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Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test.
Arvind Jain
Sundarrajan Subramanian
Rubin A. Parekhji
Srivaths Ravi
Published in:
J. Low Power Electron. (2011)
Keyphrases
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low power
single chip
high quality
low cost
power consumption
vlsi architecture
low power consumption
logic circuits
high speed
digital signal processing
power dissipation
mixed signal
low complexity
cmos technology
power reduction
gate array
design process
high power
image compression
wireless transmission