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At-speed capture power reduction using layout-aware granular clock gate enable controls.

Raashid ShaikhPradeep WilsonKhushboo AgarwalH. V. SanjayRajesh TiwariKaushik LathSrivaths Ravi
Published in: ITC (2014)
Keyphrases
  • power reduction
  • power consumption
  • high speed
  • low power
  • power dissipation
  • cmos technology
  • power saving
  • energy efficiency
  • real time
  • query processing
  • rough sets