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A generic low power scan chain wrapper for designs using scan compression.
Amit Sabne
Rajesh Tiwari
Abhijeet Shrivastava
Srivaths Ravi
Rubin A. Parekhji
Published in:
VTS (2010)
Keyphrases
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low power
low cost
high speed
power consumption
logic circuits
feature selection
single chip
high power
nm technology
wireless transmission
digital signal processing
low power consumption
delay insensitive
image compression
signal processor
gate array