Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.
Shusuke YoshimotoTakuro AmashitaD. KozuwaTaiga TakataMasayoshi YoshimuraYusuke MatsunagaHiroto YasuuraHiroshi KawaguchiMasahiko YoshimotoPublished in: IOLTS (2011)