Keikichi Tamaru

Publication Activity (10 Years)

Years Active: 1978-2000
Publications (10 Years): 0

Publications

Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru
A method for linking process-level variability to system performances. ASP-DAC (2000)
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC (1999)
Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru
Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. ICASSP (1998)
Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
Model-adaptable MOSFET parameter-extraction method using an intermediate model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (5) (1998)
Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru
Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD (1998)
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
A power optimization method considering glitch reduction by gate sizing. ISLPED (1998)
Vasily G. Moshnyaga, Kazuhiro Suzuki, Keikichi Tamaru
A new architecture for in-memory image convolution. ICASSP (1998)
Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru
A memory efficient array architecture for real-time motion estimation. Systems and Computers in Japan 29 (9) (1998)
Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru
A functional memory type parallel processor for vector quantization. ASP-DAC (1997)
Vasily G. Moshnyaga, Keikichi Tamaru
A memory efficient array architecture for full-search block matching algorithm. ICASSP (1997)
Vasily G. Moshnyaga, Keikichi Tamaru
A Memory Efficient Array Architecture for Real-Time Motion Estimation. IPPS (1997)
Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
A current mode cyclic A/D converter with a 0.8 μm CMOS process. ASP-DAC (1997)
Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI (1996)
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru
A scheduling algorithm for synthesis of bus-partitioned architectures. ASP-DAC (1995)
Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
A model-adaptable MOSFET parameter extraction system. ASP-DAC (1995)
Kuei-Ming Lu, Keikichi Tamaru
A New Algorithm for Sorting Problem with Reformed CAM. ISCAS (1995)
Vasily G. Moshnyaga, Keikichi Tamaru
A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. ISCAS (1995)
Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru
Register-Transfer Module Selection for Sub-Micron ASIC Design. IEICE Trans. Inf. Syst. (3) (1995)
Farhad Fuad Islam, Keikichi Tamaru
High speed merged array multiplication. J. VLSI Signal Process. 10 (1) (1995)
Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
An iterative gate sizing approach with accurate delay evaluation. ICCAD (1995)
Kuei-Ming Lu, Keikichi Tamaru
Processing nested loop structure with data-flow dependence on a CAM-based processor HAPP. ISPAN (1994)
Farhad Fuad Islam, Keikichi Tamaru
An Architecture for Intermediate Area-time Complexity Multiplier. ISCAS (1993)
Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD (1993)
Farhad Fuad Islam, Keikichi Tamaru
High speed merged multiplication. ICASSP (1) (1993)
Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura
Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits (1992)
Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru
Branch-and-Bound Placement for Building Block Layout. DAC (1991)
M. Ohmura, Hiroto Yasuura, Keikichi Tamaru
Extraction of Functional Information from Combinatorial Circuits. ICCAD (1990)
Keikichi Tamaru, Hidetoshi Onodera
System design of a special-purpose computer for LSI design rule checking. Systems and Computers in Japan 18 (2) (1987)
Hajime lizuka, Yutaka Hayashi, Keikichi Tamaru, Hisashi Hara
Development of a high-performance universal computing element - PULCE. AFIPS National Computer Conference (1978)