A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.
Masanori HashimotoHidetoshi OnoderaKeikichi TamaruPublished in: DAC (1999)
Keyphrases
- low power
- cmos technology
- high speed
- single chip
- low cost
- logic circuits
- power consumption
- low power consumption
- power reduction
- vlsi architecture
- nm technology
- vlsi circuits
- real time
- digital signal processing
- gate array
- ultra low power
- power dissipation
- wireless transmission
- high power
- low voltage
- mixed signal
- information flow