A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers.
Vasily G. MoshnyagaKeikichi TamaruPublished in: ISCAS (1995)
Keyphrases
- low power
- single chip
- low cost
- power consumption
- power reduction
- high speed
- vlsi architecture
- low power consumption
- logic circuits
- power dissipation
- gate array
- cmos technology
- digital signal processing
- mixed signal
- vlsi circuits
- high power
- energy dissipation
- nm technology
- real time
- image sensor
- wireless networks
- design process
- general purpose
- delay insensitive
- image processing